This invention relates, in general, to thermal dissipation and electrical conductivity in semiconductor devices and, more particularly, to a vertical metal-oxide-semiconductor field effect transistor (MOSFET) device with improved thermal dissipation and lower resistivity to the flow of electrical current.
Integrating power transistors and other circuitry including complimentary MOSFETs (CMOS), bipolar and CMOS (BiCMOS), or bipolar transistors on a single semiconductor chip is a rapidly growing technology. The power transistors typically used in such an integration scheme are vertical MOSFET devices, which conventionally utilize a doped buried layer coupled to a drain contact on a top-side of the semiconductor chip. These vertical MOSFET devices with top-side drain, gate, and source contacts are known as up-drain "T" MOSFETs or up-drain TMOS. The electrical performance of the doped buried layer in up-drain TMOS devices is limited by the resistivity of the doped silicon layer that is used for the doped buried layer.
Another type of vertical MOSFET device typically used in the above mentioned integration schemes has a drain contact covering the entire bottom or backside of the semiconductor chip while the gate and source contacts are on the top-side of the semiconductor chip. However, this conventional backside drain contact limits the operation of the vertical MOSFET device to a single output device.
Accordingly, a need exists for an integration scheme that combines at least one vertical power MOSFET device with other circuitry on a single semiconductor chip. The vertical power MOSFET device should be a multiple output device, and the integration scheme including the vertical power MOSFET device should have efficient thermal dissipation and should have a simple method of manufacture.